CONTEXT

The increase of power needs in SoC is bound to both the computation and memory resources needs. Today applications, have to manipulate a large volume of data so, this increases the activity on the communication links (busses, interconnects). This increase of the activity also leads an increase of both the power/energy consumption and the propagation time. Data provided by the industry, show that the interconnect consumption can represent up to 60% of the whole SoC consumption and the propagation time of wires is higher than of gates.

To optimize these parameters, several works use coding techniques whose the goal is to decrease the interconnect activity. The main problem of these techniques (bus invert for instance) is that the improvement obtain on the bus consumption is compensated for, surely often exceeded by the codec consumption. So in most case, the state of the art techniques are not suitable or only for very long wires (several centimeter; not acceptable for SoC).

The patented technique Spatial Switching, aims to optimize both consumption & propagation time even when the codec consumption is taken into account.

TECHNICAL DESCRIPTION

The first idea of this technique is to avoid, as more as possible, some transition patterns. The second idea is to optimize, as a priority, the transition patterns which have the biggest appearance ratio. Indeed, optimize a transition pattern which appears rarely is ridiculous. The last idea is to apply only the codec on the wires that have the most important activity. In signal and image processing applications, it is the least significant bits that have the most activity; so it is not necessary to apply codec on MSB since their activity is low. Furthermore, if we do not apply the codec on MSB, we increase the consumption gain since the codec is smaller (the consumption due to the codec is proportional to its size).

The principle of our architecture is to avoid the cross transitions on neighboring wires and if a cross transition appears then the wires are switched.

The Boolean equation below represents the behavior of our optimization technique.

BENEFITS

• The codec is very simple (few transistors are needed).
  The optimizations obtained are important since the whole energy consumption (codec+bus) can decrease up to 12% compare to the original one (only bus).
  More the technology shrinks and more the bus length increases and more the energy gain is important.
  Propagation time is not degraded.

DEVELOPMENT STAGE

The technique has been applied on different technologies (130, 90 & 65nm), on different metal layer (from 3 to 7), for different bus length (from 3 to 7mm) and for different data patterns (audio, speech & image).

Results show that our optimization technique allows us to decrease the energy consumption on buses for all these parameters.

Inventors have developed SPICE models of the Spatial Switching codec for 3 technologies (130, 90 and 65nm). Furthermore, the development of an IP block is in progress and when this IP will be available, the Spatial Switching will be tested on FPGA platform.

For further information, please contact us (Ref 01842-01)